These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary  inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The DM74LS139 comprises two separate two-line-to-fourline decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications.

All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

这些夹钳高速集成电路的电路被设计在高效的译记忆或数据路由应用被使用,要求很短的繁殖延期时间。在高效的存储器这些解码器能习惯于的系统使译的系统的效果减到最小。当与高速度记忆使用了时,这些解码器的延期时间通常是存储器的不到典型的存取时间。解码器介绍
了的有效的系统延期是可以忽略的这个工具。

DM74LS138译one-of-eight排队,在条件之上在二进制的精选的输入基于了并且设定输入。活跃低并且活跃高的一个设定输入当膨胀时，减少对外部的门或inverters的需要。解码器能没有外部的inverters被实现的一24线，并且一个32线解码器要求仅仅一inverter。一设定输入能作为数据输入为多路分解应用程序被使用。

DM74LS139在一个单个的包裹组成2个分开的two-line-to-fourline解码器。活跃低设定输能作为一根数据线在demultiplexing应用程序被使用。